Electrical circuit designers often face the problem of needing to implement electrical circuits using as little space as is practical. Circuit space is often a valuable asset which needs to be conserved, and the miniaturization of electrical circuits often improves speed, reduces noise, and leads to other performance advantages. The packages within which semiconductors are housed play a large role in determining the space needed for implementing an electrical circuit because larger packages require more space.
Traditionally, semiconductors have been housed in packages which consume an order of magnitude or more area than the actual semiconductor die which represents the electrical component. Traditionally, a bottom or inactive side of the die is bonded to a substrate and wire leads are bonded to metalized pads on a top or active side of the die. The wire leads then extend out beyond the boundary of the die for a considerable distance, where they are attached to a package lead or other contact. After the wire leads are installed, a cap is formed over the die, substrate, and wire leads to protect the component and wire leads from the environment. When an electrical circuit requires several semiconductor components, the circuit requires an amount of space dictated by the components' packages and interconnections between the packages.
"Flip chip" or direct chip attachment mounting techniques are used to increase the density of electrical circuits. Flip-chip mounting techniques relate to "flipping" the die over and directly attaching the active or top surface of the die to a printed wiring board. The attachment conventionally occurs through solder bumps formed on the metalized pads of the die. Since the actual semiconductor die size is so much smaller than a typical semiconductor package, tremendous improvements in electrical circuit space requirements can result.
However, conventional flip-chip techniques are highly impractical for all but a few applications. One problem associated with conventional flip-chip techniques is that direct attachment of a die to a printed wiring board provides little opportunity for relative movement between the die and the printed wiring board. Traditional printed wiring boards are made using a substrate, such as a Teflon-glass or a polyamide, which has a vastly different coefficient of thermal expansion (CTE) than the silicon from which most semiconductor dice are made. Consequently, when the electrical circuit experiences temperature changes, the printed wiring board expands at a different rate than the semiconductor die. A solder joint may break, the semiconductor die may break, or the semiconductor die electrical characteristics may change as a result of the stresses experienced. To overcome this problem, conventional flip-chip techniques have resorted to using exotic and expensive printed wiring board substrates or have limited themselves to applications which experience relatively constant temperatures.
Another problem associated with conventional flip-chip techniques is that the geometrical scale upon which semiconductor dice have been built for numerous years is not compatible with the geometric scale available for conventional printed wiring boards. For example, the metalized pads of a typical semiconductor die are exceedingly small and may be spaced very close together. Pad dimensions on the order of 4 mils by 4 mils with a spacing of as little as 1 mil between adjacent pads are representative of many conventional semiconductor dice. Such dimensions are compatible with conventional wire bonding techniques, but current conventional printed wiring board techniques do not permit the reliable printing of conductors, traces and other features at these small dimensions.
To overcome these problems, conventional flip-chip techniques have resorted to restricting flip-chip applications to only semiconductor components which are newly designed from scratch or which are redesigned from existing components to include die pads whose geometries are compatible with printed wiring board techniques. Costs increase only a little for new semiconductor designs. However, a gigantic infrastructure of old semiconductor designs has already been prepared and proven over the years, and these existing designs represent a wealth of intellectual effort which cannot simply be redesigned without the expenditure of tremendous amounts of funds. Consequently, flip-chip techniques are currently used in those few applications which incorporate only newly designed components or which have a sufficiently large volume to justify a component redesign.
Another problem associated with conventional flip-chip techniques is that of metallurgy incompatibilities between semiconductor dice and printed wiring boards. Semiconductor dice typically incorporate aluminum (Al) bonding pads, which are suitable for metal bonding purposes. Conventional printed wiring board techniques utilize tin-lead (SnPb) solder. If tin-lead solder is brought in contact with the aluminum pads of a semiconductor die, the pads will eventually dissolve in the solder, and electrical connection with the die will be lost. Consequently, conventional flip-chip techniques first insure that pad geometries of a semiconductor die are compatible with a printed wiring board, then deposit a barrier metal over the pads, followed by a copper (Cu) layer over the barrier metal and a layer of gold (Au) over the copper. Solder bumps may then be installed over the gold. The gold prevents the copper from oxidizing, and the solder attaches to the copper without a risk of dissolving the copper. The barrier metal protects the aluminum die pad from the copper and solder. A semiconductor foundry performs the additional metalization of semiconductor dice at the wafer level, putting flip-chip techniques beyond the reach of small run applications. The additional metallization requires masks which are compatible with the existing dice, and any original performance data gathered during manufacturing cannot be guaranteed after such significant changes to the semiconductor wafer.
Another problem associated with conventional flip-chip techniques is that of installing known good parts. Preferably, only known good parts should be installed on a printed wiring board to minimize scrap and rework. The semiconductor industry has learned how to efficiently test semiconductor dice at the wafer level through the use of test probes that contact the flat metalized pads of the dice. On the other hand, solder bumped semiconductor dice cannot be tested without using exotic and expensive test probes. Consequently, either great expense must be absorbed to acquire test probes that are compatible with solder bumps, or testing must be delayed until dice are installed on a printed wiring board. By delaying testing, the number of bad installed parts increases, and the costs associated with scrap and rework likewise increase.